Blog

RISC-V and ARM solve the same instruction-set problem under fundamentally different business and design models — an open, modular, royalty-free ISA versus a licensed, vertically curated one. This post compares the two on architecture, ecosystem maturity, and total cost, identifies where RISC-V is the defensible choice for new designs, examines the narrow conditions under which migrating existing hardware pays off, and assesses the architecture's trajectory given recent industry moves.

STM32 has grown from a general-purpose MCU line into a graduated security portfolio, with recent Armv8-M parts offering hardware isolation, cryptographic accelerators, and certified secure-boot paths. This post evaluates how well that portfolio maps onto the IoT threat model, how secure firmware is structured around it, and when a dedicated secure element or a different architecture is the better engineering choice.

Docker packages an application together with its dependencies into a portable, self-contained image that runs as an isolated process on a shared host kernel. This post explains the container model, contrasts it with full virtual machines at the mechanism level, and covers the practical operation of containers: their lifecycle, how they exchange data with the host filesystem and network, and how a running container is configured, bounded, and inspected from the host. It also walks through consuming public images, building and publishing a custom one, and the cases where containers are the wrong abstraction.

The BQ25792 is an integrated buck-boost battery charger with power-path management that handles charging and uninterrupted system supply from one device. This post examines its role at the front end of a battery-powered Jetson-class board, with practical treatment of a ~20 V DC input stage, the external selection FETs and protection the charger needs, the post-regulation to a clean 5 V, and — looking past the compute module itself — the complete carrier-board rail tree that feeds HDMI, USB, display, and logic peripherals.

In a duty-cycled STM32L1 design, battery life is set by the shape of a single repeating current-vs-time waveform: a long low sleep floor, a brief wake-up transient, and a short active burst. This post treats firmware optimization as the problem of minimizing the area under that curve, working through how sleep-mode depth, wake-up latency, peripheral consumption (ADC, voltage reference, PLL, timers, I/O), and the internal-RC-versus-32.768 kHz-crystal decision each reshape one segment of it. It closes with the arithmetic that turns a wake/sleep duty cycle into an average current and a defensible battery-life estimate.

Raspberry Pi is frequently filed under "hobbyist hardware," yet by 2024 the majority of its output went into commercial and industrial equipment rather than classrooms or workbenches. This post examines the technical basis for that shift — the Compute Module form factor, long-term availability guarantees, and modular radio certification — and sets out, with equal rigour, the domains where the platform remains the wrong engineering choice.

YAML is a human-readable data serialization language built for hand-edited configuration and structured data. This post covers its origins, how it compares syntactically to JSON, XML, and INI for the same configuration, how the three structured formats handle data typing, and the concrete places — from Zephyr build manifests to Home Assistant automation files — where embedded and electronics engineers are required to work with it.

On-chip interconnect standards like AXI dominate FPGA design, but full protocol compliance is frequently more than a given block requires. This post compares the common memory-mapped and streaming interconnects, identifies the single handshake primitive they share, and examines when a minimal hand-written interface — particularly around FIFO producers and consumers — is the sound engineering decision rather than instantiating a heavyweight standard end to end.

The electronic design automation (EDA) market for schematic and PCB design is polarizing into a small set of expensive professional suites and a fast-maturing open-source alternative. This post weighs Altium Designer, Cadence, Siemens, Autodesk, KiCad, EasyEDA and DipTrace on capability and licensing, explains the forces behind KiCad's rapid progress, and analyzes how the choice of tool propagates into the fabrication data hand-off.

Choosing a desktop application framework is less about which toolkit renders the nicest button and more about reconciling licensing cost, language ecosystem, deployment footprint, and the framework's expected direction over a multi-year product life. This post compares the .NET family (WPF, WinForms, MAUI, plus the third-party Avalonia), the Qt ecosystem (notably PyQt and PySide), Electron, Tauri, and Flutter across those axes, with emphasis on the licensing and language characteristics that most often dominate the decision.

A consideration of what actually drives camera choice for machine vision on the NVIDIA Jetson Nano. Rather than a checklist, it examines how the module's Maxwell-class compute and single-port I/O shape the trade-offs between MIPI CSI-2, USB3 Vision, and GigE Vision, and where industrial families such as the Basler ace fit into that picture.

Over little more than a year, Meta's Llama series moved open-weight language models from a leaked research artifact to the default substrate of an entire ecosystem. This post traces that arc — LLaMA 1, Llama 2, Code Llama, and Llama 3 — alongside the fine-tuning, quantization, and inference tooling that grew around it, and closes with a forward-looking forecast of where open-LLM development appears to be heading.

The RP2040's Programmable I/O block is frequently described as "bit-banging done right," but that framing understates it. This post examines the PIO execution model — state machines, shift registers, autopush/autopull, and DMA pacing — and works through concrete code fragments for LED timing, deterministic capture, pulse-train generation, complementary motor-drive PWM, and multi-machine synchronization. It then compares PIO against the fixed peripherals of a conventional STM32F-class MCU and against CPU bit-banging across several demanding I/O tasks, distinguishing where PIO is merely preferable from where it is the only feasible option.

The RP2040 is Raspberry Pi's first in-house silicon: a dual-core Cortex-M0+ microcontroller with 264 KB of SRAM, no internal flash, and a distinctive Programmable I/O (PIO) block that lets engineers implement custom hardware interfaces in software-defined state machines. This post covers what the RP2040 introduced, where it fits in embedded design, its trade-offs against conventional MCUs, and the capabilities of the PIO subsystem in detail.

STM32 advanced-control timers provide the center-aligned complementary PWM, hardware dead-time insertion, and break-input protection needed to drive 3-phase bridges, while general-purpose timers in encoder mode and the integrated ADC/comparator chain close the position and current loops. This post maps STM32 peripherals to motor types (BLDC, PMSM, stepper, brushed DC), the position sensors they pair with (Hall, quadrature/absolute encoders, resolvers), the dedicated STM32G4 and STSPIN32G4 devices, and the direct relationship between timer clock frequency and control resolution, with one compact HAL example.

In a multi-core system each core caches copies of shared memory, and without a coherency mechanism those copies diverge, causing one core to read data another core has already overwritten. This post explains the origin of the problem, contrasts hardware coherency (snoop/directory protocols, MESI/MOESI, ARM ACE/CHI) with the non-coherent reality of most heterogeneous embedded designs, separates coherency from memory ordering, and gives cache-aware C patterns for DMA buffers, false-sharing avoidance, and barrier/atomic usage.

Crossing a signal between two unrelated clock domains exposes receiving flip-flops to setup/hold violations and metastable resolution, which standard zero-delay RTL simulation does not model. This post covers the failure mechanism, the three canonical synchronization structures (two-flop synchronizer, handshake, asynchronous FIFO) with Verilog and VHDL implementations, why functional simulation produces false confidence, and a consolidated set of design rules for CDC closure.

Latency and throughput are distinct, often competing objectives in embedded data pipelines, and optimizing one frequently degrades the other. This post covers how to measure both with cycle-accurate tooling, how to model a pipeline using Little's Law and bottleneck analysis, and where to look for optimization headroom depending on whether the design target is maximum data rate or minimum response delay.

IEC 61508 and ISO 26262 rarely prescribe code directly; they impose integrity-level targets that propagate into concrete obligations on language subset, architecture, runtime diagnostics, and verification rigor. This post traces that propagation from SIL/ASIL down to the C you write, the self-tests you add, and the structural coverage you must demonstrate.

A practical walkthrough of the STM32/Cortex-M boot path, from the hardware-automatic load of the stack pointer and reset vector through SystemInit(), .data/.bss setup, and C-library initialization, ending at main(). The post emphasizes the configuration-dependent steps — clock and flash latency, power scaling, FPU, caches, external memory, watchdogs, and TrustZone — that silently break firmware when overlooked.

Dynamic allocation is banned in safety-critical embedded code because it trades determinism for flexibility — a bad bargain when worst-case timing and decade-long uptime are certification requirements. This post covers the concrete failure modes of malloc(), the pitfalls that static allocation quietly reintroduces, the patterns that actually hold up in the field, and how Rust, C++, and Ada/SPARK change the calculus.

EMC is routinely framed as a board-layout and shielding discipline, but firmware quietly sets edge rates, gates clocks, schedules switching events, and decides how a system reacts to corruption — all of which directly move radiated emissions and ESD survivability. This post examines the specific software decisions that shift spectral peaks and harden a device against electrostatic upset, with concrete code patterns and the trade-offs they impose.

A practical examination of how DMA controllers decouple data movement from instruction execution, and why their architecture is now a first-order design concern rather than a convenience. The article covers DMA fundamentals, then surveys modern controller features — linked-list descriptors, 2D addressing, request multiplexing, and security domains — in the context of gigabit-class peripherals.

A practical survey of hardware security building blocks on modern MCUs: how secure boot chains of trust, isolated key storage, and ARM TrustZone-M are actually implemented across major silicon vendors. The post compares concrete product families, maps each mechanism to real use cases, and details the fault-injection, side-channel, and logical attack classes that defeat them in the field.

Partial Reconfiguration lets an FPGA swap a portion of its fabric at runtime while the rest of the design keeps operating. This post explains what Dynamic Function eXchange (DFX) is genuinely useful for, how the AMD/Xilinx flow works in practice, how Intel and Microchip compare, and the floorplanning, timing, and isolation problems engineers must solve to ship it.

Choosing between an RTOS and bare-metal firmware is one of the most consequential architectural decisions in embedded development — yet it is frequently made on habit or toolchain familiarity rather than technical merit. This post examines the concrete overhead introduced by an RTOS, the determinism advantages of bare-metal approaches, and the specific hardware and application profiles where each solution is genuinely appropriate. Engineers will come away with a framework for making this decision analytically rather than by default.